1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundancy circuit for repairing a failure in normal memory cells by replacement. More particularly, the invention relates to a configuration for shortening a test time of a semiconductor memory device having a defect repaired by performing a replacement on an internal data line (IO line) basis.
2. Description of the Background Art
FIG. 18 is a diagram schematically showing the configuration of an array portion of a conventional semiconductor memory device. In FIG. 18, the semiconductor memory device includes a memory mat MM divided into a plurality of IO unit blocks IBO to IBn along the row direction, a row/column decoder band RCB for selecting a memory cell in memory mat MM, and a data path DPH for transmitting/receiving data to/from the selected memory cell in memory mat MM. In each of IO unit blocks IBO to IBn, memory cells of 32 bits are simultaneously selected at the time of column selection. For the memory cells (32IO) of 32 bits simultaneously selected, a spare memory array and a spare IO line pair SIO for repairing a defective memory cell column are provided. To the spare IO line pair, spare memory cells in the spare memory array are coupled. In each of the IO unit blocks IBO to IBn, in defective column repairing, a defective column is repaired by replacing the corresponding internal data line pair (IO line pair) with the spare IO line pair.
In row/column decoder band RCB, a row decoder for selecting a row of memory cells in memory mat MM, and a column decoder for selecting a column of the memory cells in memory mat MM are aligned. As will be described in detail later, a word line for transmitting a row selection signal from the row decoder and a column selection line for transmitting a column selection signal from the column decoder are disposed in parallel with each other in the row direction.
Data path DPH includes a circuit for inputting/outputting data between the semiconductor memory device and an outside of the semiconductor, an input buffer and a write driver for writing data, a preamplifier and an output buffer for reading data, and a spare replacement circuit for replacing a defective column with an IO line pair to repair the defective column.
In the semiconductor memory device shown in FIG. 18, replacement with a spare IO line for repairing a defective column is executed on the IO unit block basis (IBO to IBn). Specifically, in each of IO unit blocks IB0 to IBn, normal memory cells and spare memory cells for repairing a defective normal memory cell are disposed.
FIG. 19 is a diagram schematically showing the configuration of IO unit block IB0 illustrated in FIG. 18. Since IO unit blocks IB0 to IBn have the same configuration, in FIG. 19, IO unit block IB0 is representatively shown. In FIG. 19, IO unit block IB0 is divided into a plurality of row blocks RB#0 to RB#15 along the column direction. Each of row blocks RB#0 to RB#15 is divided into a plurality of unit memory arrays UMA along the row direction. By unit memory arrays UMA aligned in the column direction, a column block CB# is formed. In FIG. 19, each of row blocks RB#0 to RB#15 is divided into 33 unit memory arrays UMAs. As column blocks CB#, therefore, 32 column blocks CB#0 to CB#31 and a spare column block SCB#0 are disposed.
In correspondence with column blocks CB#0 to CB#31, internal data line pairs (global data line pairs) GIO0 to GIO31 are disposed, respectively. For spare column block SCB#0, a spare internal data line pair (spare global data line pair) SGIO0 is disposed. In unit memory array UMA, memory cells are arranged in rows and columns. A row block RB# is selected by the row decoder in the row/column decoder band, and column selection is performed on the unit memory array in the selected row block by the column decoder disposed for the selected row block.
Global data line pairs GIO0 to GIO31 and spare global data line pair SGIO0 are shared by the unit memory arrays UMA included in column blocks CB#0 to CB#31 and spare column block SCB#0, respectively. One row block is selected, column selection is performed in the selected row block, and data in the memory cells of 33 bits including a spare memory cell data is transferred. In a row block RB#, the normal and spare memory cells are simultaneously selected and coupled to global data line pairs GIO0 to GIO31 and spare global data line pair SGIO0.
FIG. 20 is a diagram showing the configuration of IO unit block IBO more specifically. Each of the other IO unit blocks IB1 to IBn has a similar configuration. In FIG. 20, in IO unit block IBO, unit memory arrays UMA are arranged in 16 rows and 33 columns. Unit memory array UMA has memory cells arranged in 256 rows and 16 columns. In row blocks RB#0 to RB#15, spare word lines SWL0 to SWL15 are disposed, respectively. A defective memory cell row is repaired on a row block basis.
In row block RB#0, word lines WL0 to WL255 and spare word line SWL0 are disposed being shared by corresponding 33 unit memory arrays UMA. Column selection lines CSL0 to CSL15 are disposed being shared by 33 unit memory arrays UMA.
In row block RB#1, word lines WL256 to WL511 and spare word line SWL1 are disposed, and column selection lines CSL16 to CSL31 are disposed in the row direction.
In row block RB#15, word lines WL3840 to WL4095, spare word line SWL15, and column selection lines CSL240 to CSL255 are provided in the row direction and shared by unit memory arrays UMA in row block RB#15.
In each of row blocks RB#0 to RB#15, word lines, spare word line, and column selection lines CSL are provided being shared by corresponding unit memory arrays UMA. In memory cell selection, consequently, selection of memory cell row and column is executed also in spare column block SCB#0. In each of unit memory arrays UMA, according to a 1/16 decoding operation, one of 16 columns is selected and coupled to the corresponding global data line GIO (in GIO0 to GI031). Simultaneously, in spare column block SB#0 as well, a spare memory cell column is selected and coupled to spare global data line pair SGIO0.
Spare column block SCB#0 is used to repair a defective column on the row block basis in IO unit block IB0 or replace a defective global data line pair GIO. Without waiting for a result of determination whether a defective column address is designated or not, normal memory cells and spare memory cells are simultaneously selected. After the spare determination, when a defective column address is designated, the corresponding defective global data line pair GIO is replaced by the spare global data line pair SGIO0. By performing a column selecting operation before the spare determination, time for accessing a column (writing/reading of data) is shortened.
FIG. 21 is a diagram schematically showing an example of the configuration of a unit memory array UMA. In FIG. 21, unit memory array UMA includes normal memory cells NMC disposed in plural rows and plural columns (256 rows and 16 columns) and spare memory cells SMC aligned in a row. Normal memory cells NMC and spare memory cells SMC are aligned in the column direction.
Word lines WL are disposed in correspondence with the rows of normal memory cells NMC. In unit memory array UMA, 256 word lines are disposed. In FIG. 21, word lines WL0 to WL255 are disposed. To each of normal word lines WL0 to WL255, memory cells in the corresponding row are connected. To spare word line SW0, spare memory cells SMC are coupled. Normal memory cells NMC and spare memory cell SMC are aligned in each column, and bit line pairs BLP0 to BLP15 are disposed in correspondence with the memory cell columns. Each of bit line pairs BLP0 to BLP15 consists of bit lines BL and ZBL (not shown). Corresponding to crossings between word lines WL and spare word line SWL0, and bit line BL or ZBL, memory cells NMC and SMC are disposed.
For bit line pairs BLP0 to BLP15, sense amplifiers SA0 to SA15 are disposed, respectively. When activated, sense amplifiers SA0 to SA15 differentially amplify potentials of corresponding ones of bit line pairs BLP0 to BLP15 and latch the amplified potential.
Sense amplifiers SA0 to SA15 are coupled to a global data line pair GIO via column selection gates CS0 to CS15 receiving column selection signals CSL0 to CSL15. Column selection signals CSL0 to CSL15 are commonly transmitted to unit memory arrays UMA included in corresponding row block RB# as shown in FIG. 20. In unit memory array UMA, one of column selection gates CG is made conductive in accordance with column selection signals CSL0 to CSL15, and corresponding bit line pair BLP (one of BLP0 to BLP15) is coupled to global data line pair GIO via sense amplifier SA (one of SA0 to SA15).
Therefore, the memory cells of 32 bits in IO unit block IB and a memory cell of one bit in the unit memory array in the spare column block are simultaneously selected. In one memory mat, memory cells of 32xc2x7(n+1) bits and memory cells of (n+1) bits in spare column block are simultaneously selected.
FIG. 22 is a diagram schematically showing an example of the configuration of a read data path for outputting data included in data path DPH illustrated in FIG. 18. FIG. 22 shows the configuration for output data Dout0 to Dout31 of 32 bits. The read data path shown in FIG. 22 is provided for each of IO unit blocks IBO to IBn.
In FIG. 22, the read data path includes: preamplifiers PK0 to PK31 provided for global data line pairs GIO0 to GIO31, respectively, for ampliying memory cell data on global data line pairs GIO0 to GIO31 when activated; a spare pre-amplifier SPK provided for spare global data line pair SGIO, for amplifying memory cell data on spare global data line pair SGIO when activated; multiplexers MX0 to MX31 provided for preamplifiers PK0 to PK31, respectively, each for selecting either an output signal of corresponding one of preamplifiers PK0 to PK31 or an output signal of spare preamplifier SPK; latch circuits RLFK0 to RLFK31 provided for multiplexers MX0 to MX31, respectively, and each made conductive when clock signal CLK is at the L level, to pass an output signal of corresponding one of multiplexers MX0 to MX31; and latch circuits RLK0 to RLK31 provided in correspondence with latch circuits RLFK0 to RLFK31, respectively, and entering a through state when clock signal CLK is at the H level, to pass output signals of latch circuits RLFK0 to RLFK31, for outputting output data bits Dout0 to Dout31.
Latch circuits RLFK0 to RLFK31 enter a latching state when clock signal CLK goes high. On the other hand, latch circuits RLK0 to RLK31 enter a latching state when clock signal CLK goes low.
In order to set a selection path of multiplexers MX0 to MX31, the read data path includes: a spare determination circuit 500 for generating spare address signals SPADD1 to SPADD31 for designating a defective global data line pair to be replaced by spare global data line pair SGI; an OR circuit 502 for receiving a test mode spare control signal TMSPCC and a spare address signal SPADD0 and generating a spare selection signal SPSEL0 to multiplexer MX0; and an AND circuit 504 for receiving spare address signals SPADD1 to SPADD31 and a complementary test mode spare control signal ZTMSPCC, generating spare selection signals SPSEL1 to SPSEL31, and supplying the generated spare selection signals SPSEL1 to SPSEL31 to multiplexers MX0 to MX31, respectively.
Spare determination circuit 500 stores addresses each for specifying a global data line pair to be replaced on a row block basis, takes in a row block specifying address BLADD supplied when a row active command instructing row selection is applied. When a column access command R/W for instructing reading/writing of data is supplied, spare determination circuit 500 generates spare address signals SPADD1 to SPADD31 in accordance with row block specifying address BLADD. In the configuration of spare determining circuit 500, a unit memory array corresponding to a defective column or defective global data line pair is replaced by a unit memory array including a memory cell for repairing the defect, that is, a unit memory array in the spare column block.
When test mode spare control signal TMSPCC is at the H level, a mode of testing a spare memory cell is designated. In the following description, xe2x80x9cspare memory cellxe2x80x9d indicates a memory cell in the spare column block. When a spare memory cell connected to the spare word line is used in a column block other than the spare column block, the memory cell will be referred to as a normal memory cell.
In this state of spare test mode, spare selection signal SPSEL0 from OR circuit 502 is forcedly set to the H level in accordance with test mode spare control signal TMSPCC, and multiplexer MX0 selects an output signal of spare preamplifier SPK. At this time, complementary test mode spare control signal ZTMSPCC is at the L level, all spare selection signals SPSEL1 to SPSEL31 are at the L level, and multiplexers MX1 to MX31 select output signals of corresponding preamplifiers PK1 to PK31.
On the other hand, when test mode spare control signal TMSPCC is at the L level, complementary test mode spare control signal ZTMSPCC is at the H level, and spare selection signals SPSEL0 to SPSEL31 are generated according to spare address signals SPADD0 to SPADD31. When a defective bit exists, in any of multiplexers MX0 to MX31, the corresponding global data line pair is replaced by the spare global data line pair. When no defective bit exits, all spare addresses SPADD0 to SPADD31 are at the L level, and multiplexers MX0 to MX31 select output signals of preamplifiers PK0 to PK31.
FIG. 23 is a diagram schematically showing an example of the configuration of a write data path for writing data in the data path illustrated in FIG. 18. FIG. 23 also shows the configuration for one IO unit block. In FIG. 23, the write data path includes: latch circuits WLFKO to WLFK31 for latching externally applied write data bits Din0 to Din31 synchronously with clock signal CLK; a multiplexer MUX for selecting one of output signals of latch circuits WLFK0 to WLFK31 in accordance with spare address signals SPADD0 to SPADD31; latch circuits WLK0 to WLK31 for taking in and latching output signals of latch circuits WLFK0 to WLFK31 synchronously with clock signal CLK; a spare latch circuit SWLK for latching an output signal of multiplexer MUX; write drivers WDK0 to WDK31 provided in correspondence with latch circuits WLK0 to WLK31, respectively, for driving global data line pairs GIO0 to GIO31 in accordance with output signals of latch circuits WLK0 to WLK31 to generate internal write data when activated; and a spare write driver SWDK for driving spare global data line pair SGIO0 in accordance with an output signal of spare latch circuit SWLK when activated.
Latch circuits WLFK0 to WLFK31 enter a through state when clock signal CLK goes low, and enter a latch state when clock signal CLK goes high. Latch circuits WLK0 to WLK31 and SWLK enter a through state when clock signal CLK goes high, and enter a latch state when clock signal CLK goes low.
Multiplexer MUX further receives test mode spare control signal TMSPCC and selects and supplies an output signal of latch circuit WLFK0 to latch circuit SWLK in writing data to a spare memory cell,. Spare write driver SWDK is activated when a spare is hit (when a defective bit is accessed), and drives a spare global data line pair SGIO0 in accordance with an output signal of spare latch circuit SWLK.
FIG. 24 is a diagram showing an example of the configuration of multiplexer MUX illustrated in FIG. 23. In FIG. 24, multiplexer MUX includes: an OR circuit 506 for receiving test mode spare control signal ATMSPCC and spare address SPADD0; a selection circuit SX0 for passing internal data Data0 from a corresponding latch circuit (WLFK0) when an output signal of OR circuit 506 is at the H level; and selection circuits SX1 to SX31 provided in correspondence with latch circuits WLFK1 to WLFK31, respectively, and made conductive when corresponding spare address signals SPADD1 to SPADD31 are at the H level to pass internal data bits Data1 to Data31 from the corresponding latch circuits.
Selection circuits SX0 to SX31 have the same configuration and each include an inverter IV for receiving an output signal of OR circuit 506 or a transfer control signal being a spare address, and a transmission gate TM selectively made conductive according to the transfer control signal and an output signal of inverter IV to pass a corresponding internal data bit Data. An output signal of OR circuit 506 is supplied as a transfer control signal to selection circuit SX0, and spare address signals SPADD1 to SPADD31 are supplied as transfer control signals to selection circuits SX1 to SX31, respectively.
In the configuration of the multiplexer shown in FIG. 24, when test mode spare control signal TMSPCC is at the L level, OR circuit 506 operates as a buffer circuit. Therefore, according to spare address signals SPADD0 to SPADD31, internal data bits Data0 to Data31 from latch circuits WLFK0 to WLFK31 shown in FIG. 23 are selectively passed, and an output signal Out is generated and supplied to spare latch circuit SWLK (refer to FIG. 23). When no defective bit exits, all spare address signals SPADD0 to SPADD31 are at the L level, and all selection circuits SX0 to SX31 enter an output high impedance state, so that internal write data is not transmitted to spare global data line pair SGIO. When a defective bit exits, a corresponding spare address SPADDi goes high, a corresponding selection circuit SXi is made conductive, internal data bit Datai from a corresponding latch circuit WLFKi is selected, and the output signal Out is generated and supplied to spare latch circuit SWLK.
When test mode spare control signal TMSPCC is at the H level, irrespective of a logic level of spare address signal SPADD0, an output signal of OR circuit 506 goes high, an internal data bit Data0 from latch circuit WLFK0 shown in FIG. 23 is selected, and output signal Out is generated and supplied to spare latch circuit SWLK. When test mode spare control signal TMSPCC is at the H level, data can be written into a spare memory cell in accordance with write data bit Din0 from an outside of the device. By using test mode spare control signal TMSPCC, whether normal memory cell and spare memory cell are normal or not can be determined with respect to all bits, and a defective normal memory cell can be repaired by using a normal spare memory cell. In this description, the normal memory cell indicates a memory cell coupled to global data line pair GIO, and the spare memory cell indicates a memory cell coupled to the spare global data line pair. In the following description as well, similar definition of memory cells will be used.
In a semiconductor memory device having a redundant bit, in order to replace a defective normal memory cell by a spare memory cell, a test as described below is performed. First, test mode spare control signal TMSPCC is set to the L level. Since the defect address designating a defective normal memory cell is not programmed yet, all spare address signals SPADD0 to SADD0-31 are at the L level. In this state, a test is performed on all bits of the normal memory cells. Subsequently, test mode spare control signal TMSPCC is set to the H level and a test is performed on all bits of the spare memory cells. Specifically, by selection circuit SX0 and multiplexer MX0, the spare global data line pair is selected in place of global data line pair GIO0 to make the spare global data line pair to be accessed from the outside of the device, thereby writing and reading data to and from the spare memory cell.
In the case where it is found, from the test performed on all the memory cells of normal and spare memory cells, that a defective normal memory cell exists, when the spare memory cell for replacing the defective memory cell is not defective, the defective normal memory cell is replaced by the spare memory cell (that is, the defect address is programmed in the spare determining circuit). In the replacement by the spare memory cell, in the above-described configuration, redundancy replacement is performed on a global data line pair GIO basis. Redundancy replacement for repairing a defect may be performed on a column selection line unit. As shown in FIG. 19, spare word line SWL is used, and defect repairing is executed on a word line by word line basis. In the redundancy replacement, therefore, a predetermined number of normal memory cells related to the defective normal memory cell are simultaneously replaced with the spare memory cells for repairing defect.
In the case of the configuration of performing spare replacement on a global data line pair unit, based on defect address information programmed by blowing a fuse element or the like in the spare determining circuit shown in FIG. 22, whether redundancy replacement is performed or not is determined. When an address of a memory cell to be replaced is input, write data bits input to the normal global data line pair to be replaced are transmitted to the spare global data line pair (in data writing mode). In data reading mode, the data bits of the normal global data line pair to be replaced are replaced with read data bits output from the spare global data line pair, and the defective normal memory cell and normal memory cells related to the defective normal memory cell are replaced by the spare memory cells. Equivalently, the global data line pair is replaced by the spare global data line pair.
In order to perform the repair by redundancy replacement of a defective normal memory cell, as described above, all the normal and spare memory cells have to be tested. For this purpose, test mode spare control signal TMSPCC is used. In the memory array, however, although the spare and normal memory cells are simultaneously selected in column selection, after performing the test on the normal memory cells, a test is performed on only the spare memory cells. Consequently, test mode spare control signal TMSPCC has to be switched. For the switch of the test mode, a test mode sequence requiring a predetermined time is necessary.
Specifically, for example, in order to switch the test mode for the normal memory cells to that for the spare memory cells, first, whether the test on all bits of the normal memory cells has been completed or not is determined, and after that, the test on the normal memory cells is completed. After completion of the test on the normal memory cells, a test mode for the spare memory cells is newly set, row and column addresses of the spare memory cell are generated, and a test is performed on the spare memory cells. Therefore, a certain time is required to switch the test mode, and a problem that the long test time for detecting a defective bit is necessary occurs.
Since the different tests for the normal and spare memory cells are performed in different modes, there is a problem that the test time is long. Particularly, in the case of using the unit memory array having the same configuration as that having the normal memory cells is used as a spare memory array, the number of bits of the spare memory cells increases, so that the test time on the spare memory cells increases.
An object of the invention is to provide a semiconductor memory device capable of efficiently performing a test on a memory cell.
Another object of the invention is to provide a semiconductor memory device having shortened test time for repairing an defective bit.
Further object of the invention is to provide a logic merged memory in which a logic and a memory are formed on the same chip, capable of efficiently performing a test for repairing an defective bit in a short time.
Further another object of the invention is to provide a semiconductor memory device of a type of repairing an defective bit by IO replacement, capable of performing a test for repairing an defective bit in a short time.
A semiconductor memory device according to the invention includes a normal array having normal memory cells arranged in a matrix of rows and columns, and a spare array having spare memory cells arranged in a matrix of rows and columns, for repairing a defective cell in the normal memory cells by replacement. The normal array is divided into column blocks in unit of a predetermined number of columns.
The semiconductor memory device according to the invention further includes: a plurality of normal internal data lines disposed in correspondence with the column blocks and each coupled to a selected column of a corresponding column block; a spare internal data line disposed in correspondence with the spare array and to be coupled to a selected column of the spare array; a plurality of normal data terminals for receiving external data, disposed in correspondence with the plurality of normal internal data lines; a spare data terminal for receiving external data, disposed in correspondence with the spare internal data line; and a test control circuit for electrically coupling the plurality of normal data terminals and the plurality of normal internal data lines and for electrically coupling the spare internal data line and the spare data terminal in response to a test mode instruction signal.
According to another aspect of the invention, in a semiconductor memory device for repairing a defect in a unit of an IO line disposed commonly to memory cells in a plurality of columns and coupled to a selected column, a data terminal dedicated to spare data is provided separately from a normal data terminal, and a spare IO line and a spare data terminal are coupled to each other in a test mode, so that a normal memory cell and a spare memory cell can be accessed in parallel from an outside of the device.
By providing the spare data terminal for inputting and outputting spare data, the normal and spare memory cells can be accessed in parallel, and a test can be performed simultaneously on the normal and spare memory cells. Consequently, it is unnecessary to perform tests by separate sequences for the spare memory cell and for the normal memory cells. The time for switching the sequences also becomes unnecessary. Since the spare and normal memory cells are simultaneously tested in one test sequence, the time for the test on memory cells to repair a defective bit can be greatly reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.